private linking service
PEEPLNK
AVSREQ-204811 COVERAGE_COVERGROUP xmsim internal exception "sslu_shm_sv_reg_create_type - unknown/unsupported VST_T_*"
AVSREQ-205371 COVERAGE_INTERFACES *E,COVUMF: Could not open file icc_1390bd61_7cd57bfa.ucm" for writing (ofstream exception). Error while running regressions
AVSREQ-209574 DMS_ANALOG_ELAB Standalone xrun sim is completing. On introducing Analog, block xrun gives "xmsim: *F,Interr: internal Exception" error.
AVSREQ-212761 DMS_ELAB xmelab crash
AVSREQ-212234 DMS_ELAB xmelab: *F,INTERR: INTERNAL EXCEPTION by using -newperf in AMSD-FX
AVSREQ-200084 DMS_ELAB misleading AMSAOIW warning
AVSREQ-172340 DMS_ELAB Tool is crashing with error message csi-xmelab - CSI: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-214194 DMS_LICENSE Simulation time message to be added similar to xmelab: *N,MSFLON: for DMS is getting triggered and DMS license will get checked out.
AVSREQ-207144 DMS_LICENSE Skipping of DMSO license by using VAMS wrapper
AVSREQ-214401 DMS_LP_AMS CUVHNF: Hierarchical name component lookup failed in mixed-language, LP-MS simulation
AVSREQ-213035 DMS_LP_AMS lps_power_tchecks: vst_xfile () - expected VST_ROOT, class 32
AVSREQ-204957 DMS_LP_AMS EEnet_E_Bidir creates ripple on supply voltage in a UPF LPS AMS simulation, probably caused by $cged reading from a UPF LPS power domain
AVSREQ-197007 ELAB_SV tool is not generating the "tb_sim" snapshot for encrypted design
AVSREQ-195060 GLS_GENERAL The simulation result differs with/without -disctran option.
AVSREQ-207439 LP_1801 Why xcelium does not do the force operation after power up?
AVSREQ-205784 LP_1801 $xm_mirror_force is not applied immediately after power-up.
AVSREQ-201212 LP_1801 NEW FLOW: LP liberty in compile stage - new compile error Mixing of ansi & non-ansi style
AVSREQ-200074 LP_1801 indago probe crashing during sim time
AVSREQ-209707 LP_BUILD_PERF Overhead in pwrImDmnStructTwo checkpoint
AVSREQ-200352 LP_BUILD_PERF 7x build time with LP compared to RTL only
AVSREQ-209789 LP_LIBERTY MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-203023 LP_LIBERTY LP new liberty flow: when -lps_pa_strict switch is used, this module gets classified as nonPA instead of PA
AVSREQ-213467 MSIE_ELAB Tool Crash in DSS flow while switching the XLM release
AVSREQ-213948 SIM_PERFORMANCE function error issue on "always" block execution
AVSREQ-209391 SIM_PERFORMANCE Simulation stuck at 0ns
AVSREQ-207871 SIM_PERFORMANCE elaboration FATAL - cu_xuafillot - elwait block with no count
AVSREQ-204746 SIM_PERFORMANCE Xcelium exits unexpectedly with new version
AVSREQ-204073 SIM_PERFORMANCE Fatal during elab: cu_xuafillot - elwait block with no count
AVSREQ-207469 SIM_SV_VHDL SV module port mapping to input port VHDL OOMR makes it U
AVSREQ-201538 SIM_SV_VHDL Buffer output showing "U" but input is toggling.
AVSREQ-206898 SIM_TCL #This is a comment - not working in Xcelium TCL
AVSREQ-206179 SIM_VHDL *E,TRINDXC: index constraint violation in VHDL code
AVSREQ-210924 SIM_VHPI VHDL alias to signal in waveform
AVSREQ-187699 SIMVISION_MS Rendering of transistors in schematic tracers with drain towards up, source towards down, gate towards left
AVSREQ-203869 SIMVISION_TCL Scripting of Simvision formatting save command does not work well in customer environment
AVSREQ-215855 SIMVISION_WAVEFORMS Simvision hides text if the signal or background color is changed
AVSREQ-210706 SIMVISION_WAVEFORMS VHDL enum values are not displayed anymore
AVSREQ-206872 SV_CODEGEN Customer test failed after moving from 22.03.v006 to 23.03.v004
AVSREQ-201324 SV_CODEGEN Compiler stops responding in 2303-002 : gq_cfjb - loop back corruption
AVSREQ-212104 SV_LET xmelab: *E,SOSSZI when the slice size is specified correctly.
AVSREQ-200347 SV_RUNTIME run -adjacent (stepping over a line of code) is taking a really long time
AVSREQ-93922 SV_RUNTIME RMEMEOOR: Random values in error message shown in simulator
AVSREQ-202579 VHDL_CODEGEN Fatal error when VHDL 1993 code is compiled with the -v200x
AVSREQ-202129 VHDL_CODEGEN alias to an element of an array causes internal error: MESSAGE: gq_shapecheck - ic1 null
AVSREQ-211910 VHDL_PARSE *F,INTERR: INTERNAL EXCEPTION when overloading the XOR operator
AVSREQ-202127 VHDL_PARSE xmvhdl_p segmentation fault from alias to array element in a generate
AVSREQ-212957 VPI_GENERAL SIGSEGV in sslu_with_local_trdrv_method_num of ipi_cbForce_cuf_int
AVSREQ-209925 VPI_GENERAL Need to use VPI to read allthe member variables of a SystemVerilog classobject, including those defined in the base class
AVSREQ-209834 VPI_GENERAL SIGABRT in ipi_normalizedSubHandleByIndex
AVSREQ-208471 VPI_GENERAL No textref visible for array when used with array methods
AVSREQ-210004 VPI_LWD struct elment in $stable expression does not get added to contributing signal
AVSREQ-209062 VPI_LWD Show Contributing Signal does not show contributing signal of OOMR in assertion
AVSREQ-210055 VWDB_XCELIUM Simulation fatal xmsim: *F,SIGUSR in customer env due to incorrectly linking VWDB json to xmsim executable