PEEPLNK

CCRID Product Title
-------- ------------ ---------------------------
AVSREQ-150918 FUNC_SAFETY Weird "Adding ... to fault list" messages for fault_exclude
AVSREQ-155682 SPECMAN_DEBUG Internal error when using 'trace sim_write' with tick access and FLI
AVSREQ-148618 SIMVISION_MS Analog results are not found in SimVision
AVSREQ-171670 MCE_SIM_FAILURE XLM reports internal exception when running DFT pattern with MCE
AVSREQ-172874 GLS_PERFORMANCE Elaboration time degradation over 7 times
AVSREQ-169004 FUNC_SAFETY_CONCURRENT Mismatches between 2.5k and 5k injection
AVSREQ-170503 SIM_PERFORMANCE Memory explosion during elaboration on customer testcase
AVSREQ-163671 SIM_PERFORMANCE new_default_perf causes a crash in single-step MSIE
AVSREQ-163300 PARSE_PERF Xmvlog time very high for small 111 config
AVSREQ-173807 CORE_RAND Performance issue with randomisation
AVSREQ-167708 PARSE_SV vlog crash when undefined coverpoint is given in CG in CU scope
AVSREQ-165498 LP_1801 isolation location parent not honoured but self (terminalB context)
AVSREQ-170472 GLS_TIMING Give error message for AMS nets requested for simport delay
AVSREQ-155310 FUNC_SAFETY_CONCURRENT UNSUPPORTED_BLOCK: DELAY Unsupported - Expr: (VST_E_DELAY_CONTROL) Delay Type: (Blocking delay in loop)
AVSREQ-162716 SIMVISION_TCL Simvision "waveform print" unable to print multiple page size and orientation to ps files.
AVSREQ-170408 DEBUG_DESIGN_DATABASE Text ref missing from parent struct in For loop
AVSREQ-167891 MSIE_SIMULATION While doing the simulation we are facing an error. The error message looks like this: *F ,INTERR INTERNAL EXCEPTION
AVSREQ-167417 ELAB_VHDL xmelab: *F, INTERR: INTERNAL EXCEPTION
AVSREQ-126784 COVERAGE_FUNCTIONAL Multi Dimensional Arrays of covergroup instances are not supported.
AVSREQ-172771 SIMVISION_MS For mapped symbol user can't expand single signal into the block
AVSREQ-134499 SPECTRE_AMSD Spectre cannot handle complex expressions in text macro while Xcelium does
AVSREQ-166640 JUPITER_COMPILER xmelab: *F,MCEASRT: mcebuild internal error
AVSREQ-175043 DEBUG_DESIGN_DATABASE Build with lwdgen taking 3.5x more time than build with lwd_prepare
AVSREQ-169344 SIM_VHDL xmsim TRRANGEC error at time 0
AVSREQ-148427 SV_GENERAL Support of sparse array (-sparsearray) for the multidimensional unpacked array
AVSREQ-164476 JUPITER_ENGINE MC_RTL_CUST: Functional issues in always_comb during Multicore Simulations
AVSREQ-175214 FUNC_SAFETY SET faults are changed into SEU faults without notice.
AVSREQ-167242 COVERAGE_FUNCTIONAL COVECG triggered when get_inst_coverage() is used inside a forever loop
AVSREQ-151459 ASSERTION_SVA SFLNOS - Automatic variables in assertion action block are not supported
AVSREQ-171285 SIM_SV INTERR: in systf_sformatf_return
AVSREQ-161473 PARSE_SV Source information for Statement VSTs
AVSREQ-154415 DMS_SVAMS question about UDN connect module
AVSREQ-144378 SV_GENERAL Sparsearray option to work for multi-dimensional unpacked array as well
AVSREQ-164792 JUPITER_BRIDGE Simulation mismatches observed in pATPG design
AVSREQ-169113 PARSE_SV Simulation is crashing before dumping coverage model statistics
AVSREQ-170005 RAND_GENERAL RNC library needs to be compatible with efence
AVSREQ-105611 GLS_GENERAL Annotation log / SDF statistics are difficult to interpret
AVSREQ-164060 COVERAGE_ASSERTIONS Missing assertions in coverage database after changing xcelium 20x to 21.03.003
AVSREQ-177400 RAND_GENERAL csi-xmsim - CSI: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-155265 FUNC_SAFETY_CONCURRENT UNSUPPORTED_BLOCK: DELAY Unsupported - Expr: (VST_E_DELAY_CONTROL) Delay Type: (Blocking delay in loop)
AVSREQ-170640 DOCUMENTATION sndefine
AVSREQ-172127 LP_COV_VERIFY IIRAOB error in generated ALPV coverage model
AVSREQ-164169 SPECMAN_INTEF improve error message *** Error - Bit-length mismatch between the verilog variable declaration to give exact number of bit mismatches
AVSREQ-160229 PARSE_SV Simulation with Indago GUI enables to create breakpoint on empty lines
AVSREQ-149601 GLS_SDF SDFNET due to different order of conditions in HDL construct and SDF statement
AVSREQ-165162 SIM_PERFORMANCE simulation diff via gprune_elwait
AVSREQ-170080 DMS_ELAB Internal exception during elab, inhConn_build_SBgraph() should already exist
AVSREQ-173923 RAND_SOLVER XGen API crash with unimp exception
AVSREQ-164502 MSIE_ELAB Rename/Alias the confusing options - cds_implicit/cds_alternate_tmpdir
AVSREQ-167629 SAVE_RESTART_CHECKPOINT (PBSR) -path in TCL cannot be used with -open_paklib_rdonly (during SAVE )
AVSREQ-166679 JUPITER_ENGINE Internal exception in multicore sim
AVSREQ-155709 ASSERTION_SIM `xmsim': malloc(): memory corruption: 0x0000000289018ac0
AVSREQ-154076 SIM_PERFORMANCE The behavior of asynchronization reset changes when using -newperf.
AVSREQ-171691 VHDL_CODEGEN Elaboration is looping forever
AVSREQ-147992 RAND_GENERAL Distribution of SystemVerilog
AVSREQ-158944 LP_1801 support for UPF to take precedence over liberty
AVSREQ-166812 SV_GENERAL Force value not relayed to upper hierarchies
AVSREQ-150554 GLS_PERFORMANCE libctran.so increases memory usage during sim
AVSREQ-166065 SV_PERFORMANCE Method SSS_MT_MINNOW has high contribution in xmprof.out
AVSREQ-173138 LP_1801 *SE,ISOCNER for nested liberty and non-power aware model
AVSREQ-155929 ELAB_PERF gpg_sim's simtime memory footprint are larger than gpg's by 49%(nodump), 32%(vwdb)
AVSREQ-164857 LP_1801 ILLNUM error
AVSREQ-165657 SIM_CAPTURE_REPLAY Crash in Xcelium
AVSREQ-166658 POWERPLAYBACK_GENERAL Power Playback delay file translate hierarchical issue
AVSREQ-100751 SV_GENERAL Simulator incorrectly resolves undeclared struct element to parent module struct
AVSREQ-167732 VST_PRIME xmelab INTERR with -xform_lite For_generate_always_01
AVSREQ-162381 SIM_PERFORMANCE option -disable_deadp not fixing xmelab cu_fillot - OT with streams incorrectly marked for dead PIBs
AVSREQ-169002 SV_INTERFACE USPCIP error being seen for macro in interface
AVSREQ-161421 LP_1801 MESSAGE: vst_name() - invalid class, class 688
AVSREQ-159201 IP_PROTECT_GENERAL Need support for -simulation portview/debugall with -ip1735 in xmprotect
AVSREQ-164123 MSIE_ELAB Encountered *E,CUVUNF error while implementing automsie
AVSREQ-177458 LP_SIM_PERF xmsim: *F,INTERR: INTERNAL EXCEPTION in the middle of simulation
AVSREQ-174383 RAND_SOLVER urandom_range never selects minimum value
AVSREQ-171118 DEBUG_DESIGN_DATABASE -lwd_prepare does not reduce elab overhead of -debug_opts indago_pp
AVSREQ-160087 SV_CLASSES NCLCST error on nested class type name
AVSREQ-163907 LP_1801 Please provide support for "is_pad" of liberty file.
AVSREQ-100335 SIMVISION_INFRA Simvision does not show class objects inside virtual interface also corrupting regular interface value
AVSREQ-75459 GLS_GENERAL CCMPR02172206 CCR Enhancement to dump block level SDF annotation statistics.
AVSREQ-168759 LP_1801 R&D: Enhance driver -lps: 1. full path, 2. Resolution Type
AVSREQ-171592 SV_CODEGEN Problems with string formatting and -newperf
AVSREQ-166137 LP_1801 Weird behavior with @(signal) where it goes through without any event on signal
AVSREQ-168049 DMS_SIM Access to class member through handler in resolution function should be retained in the -rnm_relax option
AVSREQ-166109 DEBUG_DESIGN_DATABASE Investigate why GUI becomes unresponsive with trace operation for wreal type
AVSREQ-172099 DMS_AMSD xmvlog_cg crash with message gq_daca_metrics - vsp switch
AVSREQ-175285 RAND_SOLVER Error message - xmsim: *F,RNDUNR: XCELIGEN assertion failed - 0
AVSREQ-167660 ASSERTION_COMPILE Extending support of -allowunderfinedsvhref to string args in assert control tasks
AVSREQ-148765 GLS_SDF SDF support in XMCLONE flow
AVSREQ-166503 LP_1801 Create attribute to specify initial block re-execution
AVSREQ-172563 MSIE_ELAB Issue an error when a bind has a wrong hierarchy at primary elaboration
AVSREQ-167332 RAND_SOLVER RNDUNR randomization internal error
AVSREQ-165779 SPECMAN_COMPILE Compilation gcc error with C generated code using string match within 'all of'
AVSREQ-172110 COVERAGE_GENERAL Coverage overwrite fails even with -covoverwrite
AVSREQ-163871 LP_1801 Automatically dump bins for state transitions without using add_state_transition in UPF
AVSREQ-162092 PARSE_SV Xcelium crash:vsc_vsc_breakable() - logical line not setup correctly worklib
AVSREQ-165553 SAVE_RESTART_DMTCP DMTCP_PATH_PREFIX exceeds dmtcp_get_restart_env()'s MAXSIZE
AVSREQ-166308 SPECMAN_GENERAL remove the requirement for incubation license for coverage callback
AVSREQ-175539 XPROPAGATION_GENERAL Simulation does not continue after breakpoint if xprop verbosity is not enabled.
AVSREQ-133390 DMS_ELAB Xcelium crashes when probing SV Dynamic types in ADE UVM environment
AVSREQ-160428 DCP Rename .xmdcp directory to .dcp
AVSREQ-166830 SV_CODEGEN Support of unpacked array of real inside unpacked struct.
AVSREQ-162403 LP_1801 Phase-1: signal corruption for inputs of a PA macro
AVSREQ-161164 CORE_RAND Randomization - SAT Solver Timeout
AVSREQ-170979 ASSERTION_COMPILE xmvlog: *E,SFLNOS: Property or sequence variables using types defined with genvars are not supported.
AVSREQ-174773 ELAB_PERF xform crash with xmclone and newperf option -enable_udp_oblit
AVSREQ-166097 PARSE_SV Getting F,INTERR with -filemap option
AVSREQ-164447 SIMVISION_MS SimVisionMS: Mixed Net Browser sort symbol is reversed
AVSREQ-167706 PARSE_SV Via Sanity crash when Covergroup is declared in CU scope and handle is given in class
AVSREQ-147921 RAND_SOLVER XGen API: Add post-post_randomize observer
AVSREQ-172692 DEBUG_DESIGN_DATABASE Array of modports appear in Indago Tops as array of interfaces
AVSREQ-172470 LP_1801 Build crash during LPX tb runs
AVSREQ-174306 LP_1801 Retention strategy is not being broken down into unique clock and reset groupings.
AVSREQ-173912 ELAB_SV Elaborator shows wrong linenumber
AVSREQ-172571 LP_INFO_MODEL_AND_QUERY Information Model returns null UPF_ISOLATION_CONTROLS handle for hybrid isolation
AVSREQ-161867 SV_INTERFACE Interface vs class assignments performance comparison
AVSREQ-171564 GLS_PERFORMANCE Gate Level Simulation : simulation time performance
AVSREQ-169062 LP_SV *SE,USPCIP couldn't guide the -lps_sv_interface_port_enh -lps_viso both usage
AVSREQ-174393 MSIE_ELAB Hierarchical name lookup error CUVUNF after updating Xcelium version to latest agile
AVSREQ-167507 HAL crashes on specific RTL; incorrectly indicates non-synthesizable constructions
AVSREQ-170614 SPECTRE_AMSD Internal exception when "value -flow" is invoked through simulator_command option
AVSREQ-171888 PROFILER_SIM_RUNTIME Profile shows "engine support" in Stream Counts section
AVSREQ-168846 SIM_PERFORMANCE Memory corruption with Xgen API + coverage + LOD
AVSREQ-168972 SV_DPI xmsim SIGUSR showing symbols from xcelium
AVSREQ-142054 SV_PORTS TYCMPAT, port connections with actual as logic[3:0] b1[2:0] and formal is a enum of logic[3:0]
AVSREQ-163961 VHDL_PERFORMANCE TRINDXC when using generic in array
AVSREQ-161425 SYSC_GENERAL Need Xcelium SystemC to ignore unconnected ports instead of giving error
AVSREQ-162673 DMS_BIND AMS : Re-enable "-relax_svbmuf" along with "-relax_svbtis"
AVSREQ-166314 SIM_PERFORMANCE xmsim INTERR in 21.09.v002 but not 21.09.v001
AVSREQ-170951 VST_PRIME Simulation Performance Impact With Nested Assertions in Generate Blocks
AVSREQ-172744 SIM_PERFORMANCE 911 Escalation: 30% increase in Elab time
AVSREQ-178939 VPI_GENERAL Simvision crashing when resizing source browser window in post-process
AVSREQ-155986 SV_LET *E,LTEANE Arbitrary expression in let actual is not supported in phase 7.
AVSREQ-168661 SIM_SV xmsim: *E,MEM25: Object is not a reg type.
AVSREQ-164333 SIM_PERFORMANCE sim crash: csi-xmsim - CSI: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-174934 LP_MSIE Generate Error Message if the user tries to run LP SIM with -genreplicated_top
AVSREQ-168134 JUPITER_COMPILER INTERR :: Exited due to errors in Multicore Code Generation - for ZD setup
AVSREQ-171534 RAND_GENERAL Unable to solve because of the conflict with values solved in Phase 0
AVSREQ-172586 ELAB_PERF Make the option -enable_vst_ifw_reduce default
AVSREQ-176502 ELAB_PERF Crash on 12th Aug nightly agile with -enable_portbit_select_opt: 3rd Aug nightly agile works fine
AVSREQ-149738 IP_PROTECT_GENERAL How to encrypt RTL code with module and its ports viewed in the encrypted code
AVSREQ-163652 GLS_SDF SDF Annotation is breaking IO realnet connections
AVSREQ-170426 COVERAGE_FUNCTIONAL CGIMNS: Multi Dimensional Arrays of covergroup instances (Inside the class) are not supported
AVSREQ-166966 XPROPAGATION_GENERAL *W,XPNODC Warning is seen during simulation in spite of giving -ENABLE_XP_DEBUG_CODE in Primary elab in MSIE flow
AVSREQ-174602 LP_1801 Inverter not working properly
AVSREQ-162808 VHDL_GENERAL VHDL ?? function should be moved to std_logic_1164 library from std_logic_1164_additions
AVSREQ-168084 DEBUG_DESIGN_DATABASE 1.35x overhead observed w/ -lwdgen (for superunit block)
AVSREQ-171735 LP_1801 ASRTST failure due to -ENABLE_LPS_WSHARE_OPT switch
AVSREQ-149956 SPECTRE_AMSD use spectre_root to find spectre lib dir.
AVSREQ-175730 LP_LIBERTY LPLIBNOF message not generated for .cdb file specified with incorrect path
AVSREQ-174956 SV_INTERFACE Issue with assignment if part-select of enum with typedef is used
AVSREQ-167968 PARSE_SV CUINDN issued at customer end.
AVSREQ-150601 SIM_SV Can Xcelium directly support force/release to a ref port ?
AVSREQ-168736 PARSE_SV Derived parameterized class encountered xmelab INTERNAL EXCEPTION
AVSREQ-171949 COVERAGE_CODE VHDL expression coverage does not show with 'set_expr_coverable_statements all'
AVSREQ-155390 ELAB_BIND Request to report -libverbose in a separate log than xrun.log file
AVSREQ-167427 SIM_PERFORMANCE INTERNAL EXCEPTION - tl_rwait_disqualify - DYNWAIT not set
AVSREQ-170900 GLS_SDF Sim crash in GLS SDF simulations - when forcing of 0 on a models AVSS power port. Not an issue in 0DLY non annotated sims.
AVSREQ-151423 COVERAGE_FUNCTIONAL xmvlog: *E,VIFCNG (testbench.sv,18|58): Virtual interface declaration is not allowed here [SystemVerilog].
AVSREQ-170087 ELAB_SV Crash with unknown type for reg
AVSREQ-171535 LP_COV_VERIFY Dump a note when add_power_state does not have -simstate to help in debugging
AVSREQ-175394 IP_PROTECT_GENERAL Multiple definitions of OpenSSL functions found in ncprotect lib while integrating OpenSSL with Import.
AVSREQ-177705 SV_PARAMETERS xmelab INTERR sv_seghandler when automatic function passed localparam that matches input size declared
AVSREQ-171379 SIMVISION_MS Current browser shows No Value Available
AVSREQ-164334 SAVE_RESTART_GENERAL save/restore not honoring plusargs on a warm restart
AVSREQ-164313 SIMVISION_DB_UTIL EXPORT: The database file could not be exported. Error with simvisdbutil.
AVSREQ-170889 DCP "publish" needs to be manually linked
AVSREQ-138083 DEBUG_DESIGN_DATABASE no source annotation in Indago lwd mode
AVSREQ-166697 LP_ISOLATION set_isolation -elements {} with a terminal boundary sink is being incorrectly filtered
AVSREQ-171703 ELAB_SV xmelab: *E,NOREFSUPP : Currently ref static do not allow references to class members
AVSREQ-154015 SIM_SAIF_TCF Enhance request for SAIF for generate block
AVSREQ-168823 ELAB_PERF Build performance for Timing GLS
AVSREQ-152109 COVERAGE_FUNCTIONAL xmvlog: *E,CGIMNS multi-dimensional Array of covergroup instances not supported
AVSREQ-151343 DEBUG_DESIGN_DATABASE Indago does not obey LRM 23.3.3.5 "Unpacked array ports and arrays of instances"
AVSREQ-165594 SIM_VHDL Incorrect TRASMM error
AVSREQ-164830 LP_COV_VERIFY Dump Design Browser like hierarchy for LP coverage database
AVSREQ-155293 FUNC_SAFETY_CONCURRENT UNSUPPORTED_BLOCK: DELAY Unsupported - Expr: (VST_E_DELAY_CONTROL) Delay Type: (Blocking delay in loop)
AVSREQ-167229 DEBUG_PROBE enable_psc_opt results in probe command failing and not display "Created Probe 1" and "probe -show" is empty
AVSREQ-172318 LP_1801 create low power api for delbuf optimization to use for qualification
AVSREQ-170990 GLS_GENERAL xmelab tool Internal exception error
AVSREQ-147911 SIM_SV Add SV stack trace to ML API
AVSREQ-162595 SIM_CAPTURE_REPLAY Delay file in XMREPLAY_SIGNAL_ATTRIBUTES_FILE caused memory leak in big design
AVSREQ-163603 GLS_TIMING Support timing in Xmclone build flow
AVSREQ-170425 LP_INFO_MODEL_AND_QUERY Dump bit blasted retention elements list, in query output
AVSREQ-158666 GLS_TIMING internal exception without access w on elaboration of netlist w/ negdelays
AVSREQ-166310 SIM_PERFORMANCE Seeing "xmsim: *F,SIGUSR: Unix Signal SIGSEGV" in 222 and full config simulations
AVSREQ-145123 DMS_ELAB Need a switch to just turn off coercion for "var real" ports
AVSREQ-162692 ELAB_SV Accept string as 1st arg to $fatal
AVSREQ-170870 POWERPLAYBACK_GENERAL Enhance Power Playback generate dump waveform tcl
AVSREQ-170474 DMS_INTERACTIVE Crash in TCL value -mxnet on DRS net wit no AICM connections
AVSREQ-175616 DEBUG_DESIGN_DATABASE Elaboration freezes for days at "writing initial simulation snapshot"
AVSREQ-172229 DMS_ELAB Spectre error with non-zero-based bus in AMS simulation
AVSREQ-175921 LP_SIM_PERF Don't report internal data pin as Liberty/HDL mismatch
AVSREQ-164606 GLS_SDF interconnect and ams fix
AVSREQ-171122 ELAB_CLONE xmelab crash in superunit bench
AVSREQ-165036 SPECTRE_AMSD AMS: bus issue with sst2
AVSREQ-163541 DEBUG_DESIGN_DATABASE Indago stuck for 5 min when expanding the hierarchy tree
AVSREQ-172939 PARSE_SV xmvlog: *E,NOAUTO when passing static variable to ref static
AVSREQ-172782 RAND_DEBUG Constraint contradiction message is totally wrong
AVSREQ-164753 DMS_ELAB xmelab INTERR in reduced testcase for AVSREQ-163823
AVSREQ-165831 DMS_ELAB Fatal error when using a generate statement in VerilogAMS - tl_rwait_disqualify - DYNWAIT not set
AVSREQ-168868 ELAB_CLONE Crash in xmclone at xst_language
AVSREQ-170127 SIM_SV Any option can resolve $fopen: file name too long (1204 >= 1024) issue at xmsim stage?
AVSREQ-169211 GLS_SDF INTERNAL EXCEPTION in Xcelium 21.09 complains about parameterized bus statement
AVSREQ-163045 JUPITER_ENGINE reduce MCE DB physical memory
AVSREQ-171116 MSIE_SIMULATION Slower runtime with MSIE flow
AVSREQ-166918 LP_1801 add_renaming_rule not working for escaped name without escape character
AVSREQ-160682 GLS_GENERAL Getting *F,INTERR: INTERNAL EXCEPTION error at elab stage when running the sims in gates
AVSREQ-167094 LP_1801 Notification request for using "connect_logic_net -reconnect" on output ports
AVSREQ-150454 SIM_PERFORMANCE Not pruned always block - packed array of clocks
AVSREQ-164263 XPROPAGATION_GENERAL -enable_delbuf_with_forgen_restrict with -enable_fgb causes xmsim INTERR
AVSREQ-130139 SV_INTERFACE Support for multidimensional array of interfaces
AVSREQ-177682 SV_CODEGEN newperf switch is causing a crash
AVSREQ-166205 ELAB_SV xmelab: *W,NEGMCV: Negative multiple concatenation multiplier did not appear
AVSREQ-157351 LP_1801 use -lps_lib_alt_output_dir, if it is set independent of the dir access policy
AVSREQ-168737 GLS_PERFORMANCE Xcelium GLST sim time performance is slower than competitor
AVSREQ-164912 GLS_TIMING xmelab crash: cuv_get_netpp
AVSREQ-165821 ELAB_CLONE xmclone internal error : MESSAGE: sslu_descend - NULL sxp
AVSREQ-171783 SV_CODEGEN xmvlog_cg internal exception - gq_ltmpspan - no defn
AVSREQ-168621 ELAB_SV *E, PCANLV issue when inout ports have conditional assignment
AVSREQ-167085 SIM_PERFORMANCE Build degradation with -enable_super_prune
AVSREQ-174369 RAND_GENERAL Checkers failure on agile nightly with customer test
AVSREQ-166400 COVERAGE_FUNCTIONAL Xmsim fatal error
AVSREQ-163584 FUNC_SAFETY_SIM Unable to inject fault in vhdl code in serial fault simulations
AVSREQ-153200 COVERAGE_TOGGLE Smart exclusion of struct element excludes all other elements in the struct
AVSREQ-167933 LP_1801 In Low Power Zero delay simulation (with UPF), AND logic is not behaving correctly after power -domain off->ON case.
AVSREQ-158480 SIM_PERFORMANCE 10x simulation slowdown reported when enabling monitor
AVSREQ-166426 ELAB_PERF xmelab: *F,INTERR: INTERNAL EXCEPTION seen with -linedebug
AVSREQ-172831 SPECTRE_AMSD F,SROOTE when bsub command running AMS simulation invoked from script
AVSREQ-158665 GLS_TIMING internal exception without access w on elaboration of netlist w/ negdelays
AVSREQ-155859 PARSE_SV *E,TUSERR - when using timeunit 1ps/1ps;
AVSREQ-164422 GLS_SDF Weird SDFAND, SDFANS when applying interconnect on real nets
AVSREQ-172633 UVM_ML mltypemap internal error converting SC class with multi-dimensional array field
AVSREQ-163147 SAVE_RESTART_CHECKPOINT save restart checkpoint doesn't look in cds alternate dir first
AVSREQ-173225 SIM_PERFORMANCE Xcelium failing unless -linedebug is set on versions after 20.12.a001
AVSREQ-170957 PARSE_SV xmvlog INTERNAL EXCEPTION function chaining issue
AVSREQ-174384 RAND_SOLVER Distribution degrade reported for urandom_range under better_urandom_range
AVSREQ-171611 ELAB_PERF Report accurate peak memory usage number for Xcelium build
AVSREQ-168796 SIM_SV $swrite interpreting %% incorrectly in latest releases
AVSREQ-147940 SV_PARAMETERS Unexpected CUVNPM using static reference to a type parameter in implements
AVSREQ-162962 COVERAGE_ASSERTIONS Switched from Xcelium 20.12.001 to 21.08.001, but immediate assertions (appear in the classes) do not see in the coverage.
AVSREQ-151013 SV_LET *E,LTEANE Arbitrary expression in let actual is not supported in phase 7
AVSREQ-164059 SV_CODEGEN Elab crash fixed with disable_espo
AVSREQ-173641 SV_CODEGEN Tool crashes during build phase with 22.03 version
AVSREQ-164211 SIMVISION_MS SimvisionMS not identifying correctly internal analog hierarchies
AVSREQ-165642 JUPITER_ENGINE MC_CUST_GLST : Simulation fatal in customer design with 22.01-a001 due to Adaptive Engine
AVSREQ-162191 UVM_ML_OA_DOCS Paramerized types UVM-ML limitation should be documented
AVSREQ-162409 DMS_LP_AMS WUDNPFS error related to liberty internal power
AVSREQ-167402 ELAB_BIND Elaboration wrongly gets completed, although non-existent libraries are used in Verilog Config rules
AVSREQ-153842 SV_INTERFACE clocking output #1step drives with 0 delay
AVSREQ-161763 COVERAGE_MERGING Request for enhancement of Merging Warning messages
AVSREQ-152087 DEBUG_DESIGN_DATABASE Parameter shows wrong value in Indago when defparam is used
AVSREQ-172030 PARSE_SV xmvlog crash - move_source_chunks error message
AVSREQ-152519 DMS_ELAB Using $temperature inside VAMS file in digital simulation causes crash
AVSREQ-165656 SIMVISION_TCL waveform print simvision TCL command does not honor the options provided second time
AVSREQ-174296 LP_ISOLATION Fixing error xmelab: *SE,ILLOBJP , when SPA has only clamp_value with ports specified
AVSREQ-162812 LP_1801 Help is needed to understand LP simulation with uvm_hdl_force and -lps_force_reapply
AVSREQ-168708 ELAB_SV User intermittently sees compress_bub_read failure.
AVSREQ-162684 SV_CODEGEN xmsim: *E,RNDSQOF: Randsequence infinite production recursion, will do a break from this statement
AVSREQ-163683 PARSE_SV Please remove incorrect NBETIF warning
AVSREQ-173357 SPECMAN_E entity references to method params for specman reflection and lint
AVSREQ-104105 IP_PROTECT_GENERAL Need to display RTL ports in encrypted code
AVSREQ-145379 RAND_GENERAL scope randomize of a member of unpacked struct
AVSREQ-174422 GLS_PERFORMANCE Xcelium GLST simulation performance is slower than other tools by 20%
AVSREQ-132286 SV_LET E,LTUNSE - LET errors
AVSREQ-173139 LP_LIBERTY Liberty inside liberty is not identified in some for_generate instances
AVSREQ-167468 SIM_CAPTURE_REPLAY Xcelium crash with xmsim error
AVSREQ-173068 ELAB_SV $fatal($sformatf("psprintf")); report *E,STTINT in Xcelium but pass in VCS
AVSREQ-165799 SV_GENERAL Require enhancement to failed assertion behavior
AVSREQ-155312 FUNC_SAFETY_CONCURRENT UNSUPPORTED_BLOCK: DELAY Unsupported - Expr: (VST_E_DELAY_CONTROL) Delay Type: (Blocking delay in loop)
AVSREQ-173871 PARSE_SV User cannot get parameterized classes to compile
AVSREQ-167641 SV_CODEGEN xmvlog_cg crash - apx - can't abstract pointer
AVSREQ-168337 XRUN_GENERAL Xcelium22.01.a002 performance is worse when uvmlinedebug option is added
AVSREQ-166141 ASSERTION_SIM Ignore cover properties for ASRTPO message
AVSREQ-165508 ELAB_SV streaming operator produces parsers errors
AVSREQ-168181 SPECTRE_AMSD *F,INTERR: INTERNAL EXCEPTION related to analog signal checks via TCL value function.
AVSREQ-172334 ELAB_SV Support of always block inside static analyzer
AVSREQ-174538 XRUN_GENERAL XRUN not recording large portion of build time
AVSREQ-178500 LP_1801 Xcelium behavior is wrong when using UPF.
AVSREQ-77032 DMS_WREAL OOMR Access Stops Wreal Coercion on the Accessed Net
AVSREQ-168909 SIM_SV Getting xmsim: *F,INTERR: INTERNAL EXCEPTION in 2203 Xcelium
AVSREQ-157697 DMS_ANALOG_ELAB Spectre error at time 0 when module parameter value contains .()
AVSREQ-163009 ELAB_SV xmsim: *E,RNDERR Randomization has encountered a bug: Internal error.
AVSREQ-175588 SIMVISION_TCL page_height_number option not giving expected output
AVSREQ-168433 GLS_PERFORMANCE Options are not captured correctly in profile file
AVSREQ-164667 SV_CLASSES elab crash cu_process_ref_args_for_extended_class
AVSREQ-174586 SPECMAN_COMMANDS Frequent GCs after reload
AVSREQ-164417 SPECMAN_E wrong value at all_off thread number
AVSREQ-166386 DMS_LP_AMS tool crashes (in probing) if udn is used in SV interface in LP context at runtime
AVSREQ-169330 RAND_SOLVER RNDCNSTE for rand variable in an array index: though array index is not rand variable but index of associative array
AVSREQ-167089 SIMVISION_INFRA (XCELIUM)(RHEL8.2)"simvision waves.shm -snapshot tb_mic NG" and " simvision FSM Window NG"
AVSREQ-162597 GLS_SDF Unknown value is not rejected even if its pulse width is smaller than interconnect delay.
AVSREQ-164596 SIM_RACEDT Modify the config commands
AVSREQ-166598 CORE_RAND Internal assertion - no sizes solved
AVSREQ-166808 PARSE_SV Order of port signals seem to matter when specifying default values
AVSREQ-161226 ELAB_SV simulation internal error with Xcelium 21.09.003
AVSREQ-168894 DMS_INTERACTIVE Fix ASAN issue in rtslib/cmdmxnet.c
AVSREQ-155291 FUNC_SAFETY_CONCURRENT UNSUPPORTED_BLOCK : DELAY Unsupported - Expr: (VST_E_DELAY_CONTROL) Delay Type: (Blocking delay in loop)
AVSREQ-170228 PROFILER_SIM_RUNTIME profiler shows 50% on rts_dpi_import
AVSREQ-164419 JUPITER_COMPILER MC_RTL_CUST: Multi-core build 13x slower wrt SC on customer design, McCodegen BE taking 5hrs
AVSREQ-174477 RAND_SOLVER randcase gets stuck for long series of value calls when using better_urandom_range
AVSREQ-170620 LP_1801 Floating connection for LIBINLIB using -lps_libinlib_always_on
AVSREQ-178196 LP_1801 Force is overwritten by custom retention model
AVSREQ-154628 SV_CLASSES qualified class name causes $cast to fail
AVSREQ-163116 RAND_SOLVER Child object's pre_randomize is not called
AVSREQ-171002 LP_INFO_MODEL_AND_QUERY Query Command conflicting with Liberty Verbosity messages
AVSREQ-175892 SIM_CAPTURE_REPLAY flexibly exclude out DLAT type sequential cells from essential list denominator when calculating mapping rate
JIRA ID COMPONENT SUMMARY
AVSREQ-171525 PARSE_SV Add feature to provide report of uvm_hdl_force & uvm_hdl_deposit calls during parsing
AVSREQ-166612 SIM_SV Error during solver destructor operation
AVSREQ-175376 LP_INFO_MODEL_AND_QUERY Power Domain mirror is erroring out due to SupplyPort with same name.
AVSREQ-170918 SIM_SV SV stack trace to XGN API: wrong source for internal calls
AVSREQ-162843 LP_1801 Support for query_power_switch
AVSREQ-169192 VHDL_PARSE VHDL OOMR using alias is giving IAPHNF error
AVSREQ-165585 SV_CODEGEN Code generation internal error with user defined nettype -> Enhance wait on a SV-UDN field
AVSREQ-168460 RAND_SOLVER *E,RNDCNSTW caused by internal rand_mode(0) coming from dist constraint
AVSREQ-158797 SR_GENERATION Possible issue with classes defined in cu scope
AVSREQ-175622 PARSE_PERF -ENABLE_MEMOPT_PARTIAL_VST parser performance impact on design
AVSREQ-168274 VHDL_PERFORMANCE elab cpu performance degradation
AVSREQ-172317 DMS_ELAB connect modules lead to Cadence internal error during xmelab -> use -svams_2019 option to resolve -> -xmerror DPSVAP is not working, address it
AVSREQ-176453 VST_PRIME System function call causes crash in For_generate_assign_01
AVSREQ-167426 COVERAGE_CODE branch coverage with pragma coverage off
AVSREQ-147752 IP_PROTECT_GENERAL Unrecognized protection pragma in IEEE 1735
AVSREQ-157996 LP_SIM_PERF (LPS) LP simulation time is 5.4x than normal sim.
AVSREQ-156775 ASSERTION_SIM Simulator crash when smartlog is enabled
AVSREQ-168016 DEBUG_DESIGN_DATABASE VPI errors when launching UVM test case in post-process with LWD
AVSREQ-170505 SIM_PERFORMANCE xmelab crash causing memory explosion
AVSREQ-137842 PARSE_SV Phase2 of -enable_smart_cuscope : enable incremental build for cuscope change
AVSREQ-143982 SIM_SV ams_flex SimVision Interactive: crash when opening the Source Browser of an updated source code used with reflib
AVSREQ-160199 SV_INTERFACE CUIDUP error seen when invoking xrio
AVSREQ-166043 SV_DATATYPES WOUPSR error encountered. Enhancement in format descriptor default implementation for unpacked array.
AVSREQ-161138 DMS_QUALITY Pa* elab time increase pwrImDmnStructTwo checkpoint -> add info during build - when mixed signal is enabled
AVSREQ-171397 LP_BUILD_PERF Enhance LPS elab performance for -lps_relax_hierarchy switch
AVSREQ-162336 FUNC_SAFETY_CONCURRENT MESSAGE: apx - can't abstract pointer, 0x0cdbdb of 0x2b9cd44f33d0
AVSREQ-177308 RAND_SOLVER Order of post_randomize calls different between 22.03-v001 and 22.07.a071
AVSREQ-131969 DMS_LICENSE license problem when using process-based save-and-restart
AVSREQ-166407 RAND_SOLVER Hanging inside of a randomization call
AVSREQ-173066 VPI_LWD VPI size of multi-dim parameter is incorrect in LWD mode
AVSREQ-153918 XPESSIMISM_GENERAL Making the correction file encrypted
AVSREQ-113350 MSIE_ELAB Spurious DYNHFN in genhref flow
AVSREQ-166134 DEBUG_DESIGN_DATABASE Behavior of RCA when specific case-block description
AVSREQ-174920 SIM_SV_VHDL Compiler reports incompatible datatypes for VHDL instantiating SV with MDAs in ports.
AVSREQ-155089 LP_1801 Generate a soft error when CSN to a module is without a port.
AVSREQ-175016 DEBUG_DEP API script randomly encounters Internal Exception
AVSREQ-172904 GLS_GENERAL Drivers command issue "object doesn't have connectivity access across language domains"
AVSREQ-157261 SIM_PERFORMANCE Simulation results are different when using -enable_ff_split and -enable_async_ff_opt
AVSREQ-170619 ASSERTION_SIM assertions fired even after using disable_assert_always_if_exists
AVSREQ-161083 SV_RUNTIME Support for memory load with defval
AVSREQ-164336 SIM_PERFORMANCE Test failing with "-newperf" option
AVSREQ-160665 LP_1801 UPF_GENERIC_SOURCE null value for isolation cell as source
AVSREQ-174461 POWERPLAYBACK_GENERAL Powerplayback - replay PIs and dump new debugging files related to new mapping rate
AVSREQ-168364 PARSE_SV What are Command-line options equivalent to these environment variables ? setenv CADENCE_ENABLE_AVSREQ_6614_PHASE_1 1 setenv CADENCE_ENABLE_AVSREQ_12055_PHASE_1 1
AVSREQ-165361 LP_1801 xmelab: *SE,NOHRPTH: (LPS) No hierarchy path is found for gbl_cor_memAcc(*)*
AVSREQ-169183 RAND_GENERAL Distribution of SystemVerilog when using 22.03.a001
AVSREQ-91041 SIM_TCL Automatic exit gives no indication of problem - lack of run command
AVSREQ-165815 JUPITER_COMPILER Support different mce_build_thread_count and mce_sim_thread_count configuration during MSIE primary and incremental snapshot build
AVSREQ-168788 JUPITER_ENGINE MC_CUST: Improve MC sim acceleration (1.7x) for this pATPG Tessent ZD case
AVSREQ-175963 COVERAGE_COVERGROUP Compiler option-ENABLE_FWD_REF_CGP_INSTANCE is not working.
AVSREQ-165781 LP_1801 INTERR uParserSetortAttributes -
AVSREQ-164215 SIMVISION_MS Missing hierarchies in Design Browser
AVSREQ-161134 GLS_GENERAL cont assign ignores distributed delay with delay_mode_path and "-nospecify"
AVSREQ-165597 PARSE_SV SCU run gives internal error (fix from 157307 included)
AVSREQ-172956 ELAB_CLONE *E,CUVUNF: -xmclone doesn't support -allowundefinedsvhref resulting in CUVUNF Error
AVSREQ-170339 LP_1801 no error created for set_design_top that does not exist
AVSREQ-169196 JUPITER_COMPILER Xcelium MCE - Compilation of splits failed
AVSREQ-110894 PARSE_SV Please add a warning when users are importing packages to the compilation unit scope.
AVSREQ-164466 RAND_DEBUG Using show_engine_contradiction changes randomization
AVSREQ-170463 LP_INFO_MODEL_AND_QUERY Query Commands corrupting Xcelium DB
AVSREQ-140172 DMS_SIM UDN performance reduction compared to var reals
AVSREQ-165555 VPI_GENERAL uvm_hdl_force not working on interconnect net
AVSREQ-168064 SIMVISION_MS "SimVision may be unstable" message when browsing for mixed nets in Mixed Net Browser
AVSREQ-163394 SPECMAN_METHODOLOGY vr_ad to error when accessing unmapped address
AVSREQ-174412 PARSE_SV Wrong information in cuscope target logfile compref_verbose.txt
AVSREQ-171456 DMS_SIM Allow provision for saving IE parameters through dms_mxnet_sql option
AVSREQ-171636 LP_1801 Liberty takes precedence over UPF generates incorrect errors
AVSREQ-133658 LP_1801 Require enhancement for is_soi biasing
AVSREQ-150438 SPECMAN_ERRORS WARN_INT_UINT_SET_SEMANTICS with longuint and set with hex literals
AVSREQ-130898 COVERAGE_TOGGLE support propagation of vector exclusion at the boundary of vhdl and verilog
AVSREQ-167420 SIM_SV_VHDL (Xcelium FSDB) Could not dump port signal value for black box module
AVSREQ-166534 MSIE_ELAB Slow build time due to DEADCODE optimization
AVSREQ-147883 SV_GENERAL Datatype unsupported in constant functions
AVSREQ-165384 PARSE_SV SCU bug for `undef impact
AVSREQ-119583 SPECTRE_AMSD How to use $cds_set_temperature at specific time from digital solver ?
AVSREQ-171268 COVERAGE_FSM set_fsm_arc_scoring causing Xcelium to crash
AVSREQ-169061 XRUN_GENERAL *SE xmelab exit change when only have *SE error in xmelab exit condition.
AVSREQ-113492 RAND_SOLVER Abnormal behavior of '1 with dist
AVSREQ-170846 ASSERTION_SIM Using "-input @source script" is breaking simulation flow for assertion not found Warning
AVSREQ-152279 DMS_ELAB Need display OOMR to not make wire logic
AVSREQ-168512 LP_1801 Outputs driven to X with -lps_new_ln_support
AVSREQ-163180 SIMVISION_CONSOLE Missing Error information in Simvision Console using Reinvoke Simulator with custom xrun log filename
AVSREQ-164218 SIMVISION_MS Broken / Partial display of internal hierarchies content
AVSREQ-173206 SV_PERFORMANCE Test in new project gets stuck at time 0 for 2 more mins than old one
AVSREQ-168015 COVERAGE_TOGGLE Create warning during smart refinement when connection is not smart excluded.
AVSREQ-166806 LP_CPF Error out when -lps_power_tchecks is used with CPF
AVSREQ-163702 COVERAGE_FUNCTIONAL Tool crashing with message "MESSAGE: svh_deref - h out of bounds"
AVSREQ-160101 SIM_CAPTURE_REPLAY XMREPLAY to support frequency scaling replay
AVSREQ-162136 VHDL_PARSE xmvhdl_p: *E,UNSPUP: Unconstrained record subtype in Subprogram return type of Record/Array of Records types is not supported.
AVSREQ-170585 MSIE_SIMULATION In MSIE env, Xcelium assigns the same handle for 2 uvm objects
AVSREQ-165499 SR_XEML Create Scripts to generate xeml.json from xrun.log
AVSREQ-163051 LP_1801 UPF inside of PA should not force user to remove liberty for PA scope
AVSREQ-163776 SPECMAN_E When printing set of values of integers, do not print the word MIN/MAX_INT (UINT, LNG, etc), rather print the number in hexa format
AVSREQ-167766 XPROPAGATION_GENERAL Different Xprop behavior W/WO protected RTL
AVSREQ-163468 GLS_SDF SDFNEP: Back annotation fails due to the wrong order of the conditional sub terms.
AVSREQ-163859 LP_1801 Output of upf_generic_sink , expected isbut getting output same as of upf_generic_source
AVSREQ-161272 SIM_CAPTURE_REPLAY Internal error while using -xmreplay_file at simulation
AVSREQ-163991 PARSE_PERF xmvlog performance issue
AVSREQ-170954 XRUN_GENERAL Xrun crashes if the -Lif the file_path is not valid without an error
AVSREQ-166823 SV_INTERFACE -disable_vifc_frc_opt and -disable_vidc resolves change in simulation behavior
AVSREQ-129203 SV_GENERAL xmelab: *E,OBJTOB error: object width exceeds implementation limit (1048575 bits)
AVSREQ-158384 IXCOM Enhancement reqeust : Sort for autoHwAccessExports_*.sv
AVSREQ-166307 ELAB_CLONE supporting v2k stub module in xmclone
AVSREQ-173771 DEBUG_DESIGN_DATABASE debug_db_design grew from 4G to 13G (21.03 vs 22.06)
AVSREQ-169324 COVERAGE_CODE Unexpected hole in expression coverage
AVSREQ-162005 LP_1801 What are possible reasons when "set_isolation -source" filters ports that are driven by the given source?
AVSREQ-169042 ELAB_PERF Elab : INTERNAL EXCEPTION
AVSREQ-161658 SIM_FORCE_RELEASE xmsim fatal error : vst_xfile() - expected VST_ROOT, class 32, file: XX
AVSREQ-166680 DEBUG_DESIGN_DATABASE Creating a calculation with an enum value does not work
AVSREQ-172835 ELAB_BIND xmelab not able to find instance beginning by a number
AVSREQ-157680 DMS_ELAB CUNDCM: Incompatible real port connection when using -rnm_tech option
AVSREQ-169242 DEBUG_PROBE probe/ida_probe with non-existent path dumps entire hierarchy
AVSREQ-166923 SIM_PERFORMANCE Elaboration freezes when using 22.02.a001.
AVSREQ-173141 SV_INTERFACE xmelab crash: Message displayed - ncxxLpIllegalOomr::getAoiIndex - Invalid Selection
AVSREQ-168442 RAND_SOLVER Randomize performance issue
AVSREQ-172665 SIM_SV Need relax option for *E,PCRFNC
AVSREQ-161604 IP_PROTECT_GENERAL Compile error in xmprotect file
AVSREQ-162353 SIM_PERFORMANCE dead pib optimization is generating an internal error
AVSREQ-171565 PARSE_SV internal error in xmvlog: p4_mdecl - let body expression default
AVSREQ-162077 LP_1801 (EP Connectivity UPF PA RTL) Elaboration fails with PPSUPFM
AVSREQ-167284 SPECTRE_AMSD Performance degradation using $cgav to catch vector analog net in a digital context
AVSREQ-167690 MSIE_ELAB Long primary elaboration in single-step MSIE
AVSREQ-163980 LP_1801 Implementation: is_analog liberty/UPF attribute for isolation and corruption filtering
AVSREQ-164503 SIM_PERFORMANCE Functional inconsistency with -enable_aca_pw_bval
AVSREQ-173836 SIM_EVCD Crash in EVCD dump while using the tran primitive
AVSREQ-173649 COVERAGE_FUNCTIONAL INTERR in cov_process_cross_bins
AVSREQ-151632 COVERAGE_PERFORMANCE Internal error from xmsim when set_optimize -newperf coverage option is used.
AVSREQ-154980 XPESSIMISM_GENERAL Utility to merge correction files from multiple runs
AVSREQ-159303 DEBUG_PROBE xmsim: *F,SIGUSR: Unix Signal SIGABRT raised from user application code
AVSREQ-166374 JUPITER_COMPILER Multiple usage of -add_seq_delay or -seq_udp_delay cause fatal error in MCE
AVSREQ-169320 LP_ISOLATION Xcelium isolation insertion w/ -applies_to_boundary
AVSREQ-164064 LP_1801 Weird b2b isolations w/ one on input of PA
AVSREQ-168654 COVERAGE_CODE -unused_if_inside_pragma option is not working under pragma off region
AVSREQ-173005 SIM_FORCE_RELEASE Excessive memory consumption during simulation
AVSREQ-167208 SV_GENERAL messages to uninitialized file descriptor doesn't appear in xrun.log but appear in the smartlog
AVSREQ-167461 SIM_CAPTURE_REPLAY Early mapfile sanity check on mapping rates based on real netlist
AVSREQ-165576 GLS_SDF GLS SDF issue with SSS_FINDRFT
AVSREQ-168925 SV_RUNTIME $fread behavior for dynamic packed array : ($fread is not loading to highest address of memory as per LRM 21.3.4.4)
AVSREQ-174283 SIMVISION_MS SimvisionMS hanging with sst2 format randomly
AVSREQ-174275 PARSE_SV Error when passing unpacked structure by reference as the first function argument
AVSREQ-177939 SIM_TCL $TCLLIBPATH issue. Need Green release for 22.03-v002
AVSREQ-172129 SIM_PERFORMANCE Memory explosion during elaboration (HDC)
AVSREQ-157600 SV_GENERAL WOUPSR in AOI is not reported in single instance
AVSREQ-169003 DEBUG_DESIGN_DATABASE Driver tracing issue with an interface instance
AVSREQ-167313 JUPITER_ENGINE MC_CUST_EVAL: Allow MC simulation to pick available CPU cores on a server by not setting affinity
AVSREQ-167763 SIM_PERFORMANCE MSIE: *W,VTWPPSNT: sanity check failure for conversion attempt, with -enable_var_opt_core
AVSREQ-173919 SV_GENERAL Disabling a block while an NBA is in progress, does not update value of NBA
AVSREQ-164638 SPECMAN_E Wrong longuint argument value in 32bit compilation
AVSREQ-166146 LP_1801 Elab INTERR when LP enabled for Full Soc
AVSREQ-174771 PROFILER_SIM_RUNTIME Require file name for protected code entry
AVSREQ-164598 SIMVISION_MS Sorting and Display Count not working properly in SimVision MS Currents Browser
AVSREQ-163607 SPECMAN_METHODOLOGY UVM Testflow add end_of_phase event
AVSREQ-174176 PARSE_SV Cuscope DPI import does not get reported in CUDCLR with -parseinfo cuscope
AVSREQ-165987 RAND_PERFORMANCE Missing enum constraint causes iteration for long solve time
AVSREQ-170300 SIM_SV Get next event time except all postpone event
AVSREQ-174061 IXCOM xmsim crashes with "MESSAGE: svvi_get_stream - stream not found"
AVSREQ-174025 ELAB_CLONE Crash in xmclone at process_svbind_upscopes
AVSREQ-165926 SPECMAN_E Failure before restore completion causing seg. fault crash
AVSREQ-161519 SIMVISION_SOURCE_BROWSER Add support for debug scope, textrefs etc with -replace_path.
AVSREQ-171849 DEBUG_COMMAND Remove "-all" option of ida_database from xmsim help message
AVSREQ-160326 PROFILER_XPROF Xcelium crashes running with -xprof option in 21.03.v006
AVSREQ-164720 ELAB_SV_VHDL Xcelium 21.09 SV macro elaboration fails but passes in version 21.03
AVSREQ-162214 SPECMAN_ERRORS Indago SNI - Specman crash when abort from stop state
AVSREQ-173148 ELAB_PERF MSIE final snapshot build hangs with newperf options -enable_memopt_snap_all_modes -enable_memopt_trg
AVSREQ-158924 SIM_PERFORMANCE VTW functional mismatches not detected by VTW warnings
AVSREQ-174242 RAND_SOLVER rand values in urandom_range are just toggling between 2 values in 21.09-v005
AVSREQ-174901 SV_CODEGEN Testcase internal error : xmelab: *E,BADTMPENV: dlc_wait_for_ncvlogcg(): Cannot read MCVLOG CG stat tmpfile.
AVSREQ-140702 FUNC_SAFETY_CONCURRENT Safety Waveform should be SHM format rather than VCD format
AVSREQ-165433 SIMVISION_CONSOLE Reinvoke does not give error info when -log is used
AVSREQ-132503 PARSE_SV timeunit 1ns/1ps does not seem to be working same as timeunit 1ns and timeprecision 1ps as per LRM IEEE 1800-2017 section 3.14.2.2
AVSREQ-163624 VHDL_PARSE VHDL AMBIGE error
AVSREQ-164833 LP_1801 Adding UPF source code in IMC for easy debug
AVSREQ-177229 LP_BUILD_PERF Checkpoint LP - after UPF Parsing is very slow in customer testcase
AVSREQ-167873 FUNC_SAFETY Tool hangs in good simulation
AVSREQ-164534 SV_PERFORMANCE Simulation failing with enable_vidc option
AVSREQ-145619 GLS_SDF Part of Interconnect delay is not annotated.
AVSREQ-171790 SIM_PERFORMANCE Combination of newperf switches is causing a misbehavior in always block sensitivity
AVSREQ-176164 DEBUG_DESIGN_DATABASE Invalid index for mda in Source Browser and Waveform Viewer
AVSREQ-172847 DEBUG_DESIGN_DATABASE Cannot add signal from SimVision Source Browser
AVSREQ-173102 ELAB_BIND xmelab: *F,INTERR: INTERNAL EXCEPTION message - sv_seghandler - trapno -1 addr((nil))
AVSREQ-150176 GLS_SDF Wrong interconnect delay annotation.
AVSREQ-163280 DCP is not packing all needed files
AVSREQ-152303 DMS_ELAB Need display OOMR to not make wire logic
AVSREQ-167524 SIM_PERFORMANCE Xcelium: Elab taking longer time than competition (Phase2)
AVSREQ-164967 LP_INFO_MODEL_AND_QUERY xmsim crash by using information model task upf_create_object_mirror
AVSREQ-158704 MSIE_SIMULATION xmsim: *F,INTERR: INTERNAL EXCEPTION MESSAGE: Unexpected signal #11, program terminated (null)
AVSREQ-165139 XPROPAGATION_PERFORMANCE Simulation time overhead is 2.5x (when running Xprop)
AVSREQ-169047 DMS_INTERACTIVE Crash in TCL describe netpath with -type option
-------+-------------+------------------------------------------------------------------ -------+-------------+------------------------------------------------------------------
AVSREQ-173952 LP_1801 Support for string argument in lps_link system task
AVSREQ-157675 SIMVISION_MS Allow to Create current probes from "Browse Currents"
AVSREQ-162801 PARSE_PERF xmvlog time is very high for "relatively" small 111 config bench
AVSREQ-174350 SPECTRE_AMSD Current Browser shows incorrect current when probing the current on a bus bit net
AVSREQ-170587 COVERAGE_COVERGROUP INTERNAL EXCEPTION with coverage enabled
AVSREQ-134478 SPECTRE_AMSD Spectre cannot handle complex expressions in text macro while Xcelium can
AVSREQ-162160 DEBUG_DESIGN_DATABASE Rerunning cds-dsn-gen (without needing to re-elaborate) gives errors
AVSREQ-175083 SPECMAN_E Add API to entity_reference that returns expression strings for targets and method parameters
AVSREQ-168538 SIM_MLTYPEMAP Issue on UVC-E integration - INTERNAL EXCEPTION in MLTYPEMAP SV adapter
AVSREQ-161761 SIM_SV xmsim stuck when calling to $countdrivers
AVSREQ-159315 CORE_RAND Contradiction on array sizes with TRAT
AVSREQ-168985 SAVE_RESTART_CHECKPOINT In warm restart, save +plusarg with same name takes precedence (over restore +plusarg)
AVSREQ-115502 IP_PROTECT_GENERAL Ports are not visible when -autoprotect and -ip1735 are used combinedly
AVSREQ-166381 LP_1801 lps_ph1_inout conflict with RTL constant driver
AVSREQ-160401 SV_INTERFACE VTWFRC warning with XRIO flow
AVSREQ-153870 LP_1801 bind_checker support for creating checkers under the hood
AVSREQ-170618 LP_INFO_MODEL_AND_QUERY Enhance bind_checker under-the-hood for isolation hybrid scenarios
AVSREQ-166293 PARSE_SV Breakpoints applied in the wrong line
AVSREQ-161718 SV_PERFORMANCE flop not switching correctly when the reset went high
AVSREQ-159806 GLS_GENERAL Elab crash: cdp_wrap: unsupported cdp node: 927 at split
AVSREQ-170314 VPI_GENERAL MSIE: interface not seen in design hierarchy
AVSREQ-167874 SV_PERFORMANCE Calling big array's method of "unique()" is extremely slow
AVSREQ-143708 LP_1801 Support for query_power_switch
AVSREQ-132953 GLS_GENERAL unexpected behavior of verilog primitive
AVSREQ-164194 LP_1801 Isolation rule optimised away without an error *NOISELE
AVSREQ-168336 JUPITER_COMPILER MC_RTL_CUST: MC codegen BE crashed with -mce_rtl (next phase) in customer design
AVSREQ-170920 LP_1801 lps_query_cmd_file - bind checker retention_ppn UDFUOBJ Error
AVSREQ-170909 RELEASE_INSTALLATION Crashes with libsn.so for libxmsim.so
AVSREQ-173859 DMS_ELAB -sv_ms leads to E*NOTPAR with Xcelium 21.09 and 22.03 but not with 21.03
AVSREQ-171640 LP_SIM_PERF Enabling DELBUF for LP simulation
AVSREQ-138806 GLS_GENERAL xmelab: *F,INTERR,MESSAGE: apx - can't abstract pointer, 0x8edd610 of 0x3efc8ca8
AVSREQ-173120 RAND_GENERAL Inside constraint gets ignored
AVSREQ-173158 MSIE_ELAB In multi-xrun MSIE same handle is assigned to 2 uvm objects
AVSREQ-163278 LP_1801 UPF_GENERIC_SOURCE should not pick up as source the isolation cell that belongs to that strategy
AVSREQ-163602 COVERAGE_XMCLONE Support Coverage in Xmclone build flow
AVSREQ-118157 LP_1801 LPS Enhancement request : Support the Naming rule for GLS-LP.
AVSREQ-171615 LP_1801 Output terminal of IO cell on the Top hierarchy is an undefined value even if power is turned on.
AVSREQ-146364 ASSERTION_SVA *E, SFLNOS: Case-statement inside SVA is not supported
AVSREQ-169336 SIM_PERFORMANCE Port clock forwarding optimization to 21.09.v
AVSREQ-164551 SV_INTERFACE *E,CUIDUP error shown when "-lps_sv_interface_port_enh" is used
AVSREQ-173642 VPI_GENERAL $writememh for 2-dimensional array is not working
AVSREQ-164839 PROFILER_MEM_XPROF INTERR during simulation if using -mem_iprof
AVSREQ-94947 COVERAGE_REPORT_ANALYSIS IMC Macro Expansion
AVSREQ-163238 LP_1801 Support multi-dimension AOI in LP
AVSREQ-153531 LP_1801 Support for query_isolation key UPF_GENERIC_SOURCE
AVSREQ-167199 SV_DPI simulation time crash
AVSREQ-176100 LP_1801 Downgrade the error *E,LPSNOSN to warning message
AVSREQ-167632 PARSE_SV VIP compile fail with -ext_src_info append from debug_opts indago_pp
AVSREQ-163708 COVERAGE_CODE Block coverage on randcase is always at 0%
AVSREQ-167449 PARSE_SV Missing closing parenthesis in macro is not issuing EOFAMP
AVSREQ-169416 LP_1801 elaboration not re-executed after a change in naming rule file
AVSREQ-170346 ASSERTION_PERFORMANCE assert -off -always <> -depth all take a lot of time
AVSREQ-175967 SR_XEML Problem with relocated UCM and UCD files
AVSREQ-163277 LP_1801 UPF_GENERIC_SOURCE is returning wrong supply_set for liberty as source
AVSREQ-166167 COVERAGE_FUNCTIONAL COVNLK in covdump
AVSREQ-157339 LP_BUILD_PERF Elaboration time blow up from 30 min to 10.5 hrs if zero/singlepin retention policy is used
AVSREQ-163703 LP_1801 NOISELE for one of the 3 scopes.
AVSREQ-173323 SV_CODEGEN Crash at code generation with 22.03.a001
AVSREQ-156809 SIM_FORCE_RELEASE Simulation stuck on time 0 for 10 min when running with UPF
AVSREQ-159045 CORE_RAND xmml backdoor mode option used wrongly caused lot of issues
AVSREQ-175651 GLS_TIMING Xcelium report Internal Exception when running simulation with UPF
AVSREQ-172087 SAVE_RESTART_CHECKPOINT The tool auto-creates a snapshot directory if it does not exist, save -path
AVSREQ-170758 SR_XEML xmdb incompatible with SUSE12.5
AVSREQ-164445 SIMVISION_MS SimVisionMS: Browse Current Click and add to schematic area not working.
AVSREQ-160662 UVM uvm_hdl_force is not forcing properly vhdl variable of enum type
AVSREQ-150934 PARSE_SV RANDRARGW with std::randomize on unpacked struct
AVSREQ-160685 DEBUG_PROBE enable_psc_opt results in probe command failing and not display "Created Probe 1" and "probe -show" is empty
AVSREQ-174152 XRUN_GENERAL xmsc parsing error
AVSREQ-163094 SIM_PERFORMANCE Reset in always-statement is not evaluated correctly after power-up
AVSREQ-171472 VPI_GENERAL VPI Error Message of calling vpi_get_value with vhpi objects
AVSREQ-172456 MSIE_ELAB MSIE: IEOPMS Error
-------+-------------+------------------------------------------------------------------------------------ -------+-------------+------------------------------------------------------------------------------------
AVSREQ-175326 DEBUG_DESIGN_DATABASE -zlib 1 && -lwd_prepare in build causes -lwd_complete to crash
AVSREQ-164676 COVERAGE_PERFORMANCE Loading coverage-data takes a really long time ICC?
AVSREQ-167457 PARSE_SV Replicated assignment pattern fails under DEBUG_BIND env var
AVSREQ-163377 LP_VHDL UPF terminal boundary setting leads to glitches in the simulation (VHDL)
AVSREQ-167046 SV_PARAMETERS xmelab SIGSEGV; SV assigning a function to a localparam type
AVSREQ-148438 SV_INTERFACE 21.05.a001 INTERNAL EXCEPTION occur during elaboration
AVSREQ-167221 JUPITER_ENGINE Crash in PBBOX execution function
AVSREQ-168636 SPECMAN_E Mechanism to fix paths in compiled exe/so
AVSREQ-94948 COVERAGE_REPORT_ANALYSIS Coverage Macro Support
AVSREQ-160493 GLS_PERFORMANCE 64% time consumed in GLS-SDF setup. Need to review.
AVSREQ-161448 DEBUG_DESIGN_DATABASE Memory usage of -lwd flow is beyond 135G, need to fit in 110G
AVSREQ-165792 LP_1801 Isolation is being incorrectly inserted in power model / terminal boundary with -is_hard_macro
AVSREQ-167651 XRUN_GENERAL Enhance xrun to set stacksize
AVSREQ-174688 LP_INFO_MODEL_AND_QUERY Bit blast elements_UPF_GENERIC_ASYNC_LOAD & elements_UPF_GENERIC_CLOCK also
AVSREQ-166581 LP_SV LPS: Crash with usage of -lps_postpone_alias
AVSREQ-164351 ELAB_PERF Xcelium: Elab taking ~5hrs where the competition is taking ~1hr
AVSREQ-135847 FUNC_SAFETY_CONCURRENT Safety Waveform - dump SHM instead of VCD for fault simulation
AVSREQ-149468 GLS_SDF Incisive vs xcelium SDF annotation issue
AVSREQ-142285 DMS_SVAMS Elaborator crashes when class object is instantiated inside SVAMS connectmodule
AVSREQ-171523 LP_1801 Simulation crash with 22.05
AVSREQ-174219 JUPITER_BRIDGE Elaboration hang
AVSREQ-170874 LP_ISOLATION "set_repeater" on floating ports are not reported in lps_logfile
AVSREQ-170604 COVERAGE_COVERGROUP Covergroup not present in the UVM hierarchy as expected
AVSREQ-166558 PARSE_SV multiple files on a single line inside hdl.var LIB_MAP variable leads to syntax error
AVSREQ-162513 MSIE_ELAB MSIE : Re-enable "-relax_svbmuf" along with "-relax_svbtis"
AVSREQ-169343 SIM_VHDL xmsim TRRANGEC error when adding -access
AVSREQ-171793 LP_LIBERTY Potential False trigger of xmelab: *W,RTLBMM: [LPS] in 22.03.v002
AVSREQ-171810 SIMVISION_UVM_VIEWERS Registers are not displaying in register viewer
AVSREQ-174817 LP_ISOLATION Even after placing a repeater, corruption is not seen. Needs debugging and a fix.
AVSREQ-171588 SR_XEML [XEML] DRM jobs got stuck for xmml_learn and dataset collection
AVSREQ-171527 LP_1801 xmelab: *E,BCMBTO: [LPS] related to multi step xrun build with "-reflib"
AVSREQ-158664 SIM_PERFORMANCE enable_var_opt_core causing assertion error
AVSREQ-170984 COVERAGE_FSM xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-174263 DMS_ELAB Improve CMINHR and CUVHNF messages with instances location
AVSREQ-165818 DMS_PERF auto_svrnm_perf improve when real constant IE only
AVSREQ-160388 ESW_ESWDBGEN Indago ESW misses execution of portions of embedded code
AVSREQ-153066 SV_LET Add support for let construct in constraints
AVSREQ-173733 ELAB_PERF LPX Build Crash with -enable_portbit_select_opt option
AVSREQ-170143 GLS_SDF The interconnect delay in SDF is ignored.
AVSREQ-170959 SV_DATATYPES TRNULLID : Associative array with 'x/'z index - unexpected behavior
AVSREQ-159112 LP_1801 Lot of signals dropped isolation, where CLP places. Need to fix all those
AVSREQ-165388 COVERAGE_FSM states uncovered with Xprop while 100% block/expr
AVSREQ-168287 VHDL_GENERAL Need to move logic operator functions from std_logic_1164_additions to std_logic_1164.vhd
AVSREQ-166277 JUPITER_BRIDGE MC_CUST_DFT: MC elaboration 6x slower wrt SC on customer's ATPG GLST design
AVSREQ-167452 XPROPAGATION_GENERAL signal does not wake up (x-> 0) even during the power on stage
AVSREQ-165588 LP_1801 isolation hybrid identify wrong isolation cell for location self
AVSREQ-170115 SIMVISION_LOW_POWER Power switch missing in PSN when using for loop
AVSREQ-167569 LP_1801 strange warnings W,RECPROC in VHDL context
AVSREQ-152290 SYSC_GENERAL setting MALLOC_PERTURB_=85 blocks creations of sigusrdump.out file
AVSREQ-174879 SV_CODEGEN Internal error in customer design during code generation
AVSREQ-172676 IP_PROTECT_GENERAL Error while running xmprotect in 22.03 using pragma syntax. Works fine in 21.03.
AVSREQ-159205 SIM_PERFORMANCE Simulation got *F, INTERR when using -automsie and -msie_ms_relax_parnum
AVSREQ-166101 GLS_PERFORMANCE Need to get better performance in MBIST simulation
AVSREQ-175143 SV_INTERFACE UNINIS soft error in 22.03 and not in 21.09.v006
AVSREQ-158169 SIMVISION_MS Improve current browser to allow extracted currents on custom depth
AVSREQ-174581 ELAB_CLONE Xmclone verbosity log improvement needed for dumping clone target instance source code
AVSREQ-171507 PARSE_SV Xcelium XMDC : *E, HRAUTO with generated verilog file
AVSREQ-158083 SIM_SV can't put an instance breakpoint on a super class function
AVSREQ-172355 JUPITER_BRIDGE Internal error when building with MC
AVSREQ-172696 SV_CLASSES Elab time degradation with 21.09.v005
AVSREQ-168958 SV_GENERAL VARIST reported on covergroup initialization
AVSREQ-155290 FUNC_SAFETY_CONCURRENT Assert statement Unsupported
AVSREQ-175818 VST_PRIME VST XFORM Crash
AVSREQ-164838 SAVE_RESTART_DMTCP xrun failing on restart with no error message
AVSREQ-168809 SAVE_RESTART_DMTCP Restore in PBSR Mode Failing Due to Unopenable File
AVSREQ-139020 DMS_SVAMS -svams_2019 gives an error during compilation when including a package -> improve error message
AVSREQ-166056 SIM_PERFORMANCE Observing 10-12% slowdown in 222 and full config simulations
AVSREQ-163693 VPI_PERFORMANCE Simulation taking 13x time when fsdb dump enabled
AVSREQ-168992 VPI_GENERAL Process to find the next simulation time
AVSREQ-167470 POWERPLAYBACK_GENERAL PowerPlayback to support MBFF auto mapping on incremental netlist
AVSREQ-170625 PARSE_SV xmvlog INTERR: Null pointer handed to sfree
AVSREQ-167736 LP_1801 Async Reset asserted during COA does not cause Q to be driven to X
AVSREQ-165810 SV_INTERFACE Enhancement allow -top my_interface with -no_top_level_interfaces
AVSREQ-133467 SIM_SV Function of "Multi_driven" report at simulation.
AVSREQ-161720 XPROPAGATION_GENERAL xmsim INTERR when xprop is enabled in newer version of xcelium
AVSREQ-167290 SPECMAN_COV OS signal 11 using cover item > 32 bit with bits ignore attribute
AVSREQ-162883 IP_PROTECT_GENERAL One encryption option that encrypt RTL file except IO ports and parameters
AVSREQ-171763 GLS_GENERAL Simulation Failure *E,ERRSEV
AVSREQ-169059 GLS_TIMING Xcelium miss simulate interconnect delay with black box module
AVSREQ-150142 ASSERTION_SVA Supporting automatic variables in assertion action block
AVSREQ-171473 DEBUG_PROBE Fail in dumping VWDB with multiple system tasks of shm_probe
AVSREQ-167982 FUNC_SAFETY XFS plugins to stop adding -xmfatal FLTONF to fs_pre_param.g_elab.f
AVSREQ-172613 DEBUG_DESIGN_DATABASE Parameterized class text-refs are not working properly in post-process with LWD (works with snapshot)
AVSREQ-168866 ELAB_CLONE xmclone Crash at cu_get_vlogot
AVSREQ-163370 SV_CLASSES xmelab: *E,NCLCST Nested class datatype not currently supported as target in $cast.
AVSREQ-161644 SV_DPI Dynamically change different .so file with save&restore during simulation phase
AVSREQ-166002 ELAB_PERF Xcelium GLST build time is 2x behind compared with competition
AVSREQ-165664 LP_1801 Remove dumping DEFAULT_NORMAL and DEFAULT_CORRUPTS SS states in coverage database.
AVSREQ-164612 SIM_TCL The environment variable $TCLLIBPATH overridden by Xcelium
AVSREQ-164026 SYSC_GDB Generic payload - incomplete type in GDB
AVSREQ-170034 ELAB_SV xmelab crash with internal exception with 22.01 - Error: Error processing stack frame(2) - skipping rest of frame!
AVSREQ-100976 SIMVISION_INFRA Signals inside tasks/functions are not visible in SimVision with Xcelium
AVSREQ-164068 LP_1801 Corrupt On Activity does not corrupt sequential logic when clock changes
AVSREQ-165751 SIM_SV Xcelium tool crash with Internal Exception error (when checking the BUS parameters)
AVSREQ-128488 ASSERTION_SIM SVA Attempt count is strange
AVSREQ-168147 XRUN_GENERAL uvmlinedebug is using linedebug under the hood
AVSREQ-172573 LP_1801 is_hard_macro is not being applied to a power model / terminal boundary
AVSREQ-147855 COVERAGE_FUNCTIONAL xmvlog: *E,QAASCO Associative arrays are not supported as argument to covergroup
AVSREQ-158286 ASSERTION_SIM *F, Internal Exception: Msg : rts_abrthandler - SIGABRT unexpected violation pc=0x2aaaabbc1337 addr=0x50df6ef50002699e
AVSREQ-174494 DEBUG_COMMAND Cannot see final value in class structure window of Randomization debugger
AVSREQ-151161 ELAB_VHDL The "-roelab" option causes DLPAKW error.
AVSREQ-177763 LP_SIM_PERF Internal exception (xmsim) in LPS
AVSREQ-156490 IXCOM Using -target with xrun -hw flow causes xmsim: *F,NORUNSP runtime error
AVSREQ-167751 SIMVISION_DB_UTIL When exporting PSFXL databases to CSV format using simvisdbutil, simvisdbutil randomly gets stuck.
AVSREQ-164631 LP_1801 AND gate behavior is incorrect
AVSREQ-170590 LP_SV internal error seen when trying to use bind_checker
AVSREQ-171381 COVERAGE_COVERGROUP E,DUPIDN identifiers of coverpoints
AVSREQ-175403 LP_1801 xmelab: *F, INTERR MESSAGE: apx - can't abstract pointer
AVSREQ-173308 SIM_PERFORMANCE XMELAB crash due to a coverage control file entry.
AVSREQ-175138 ELAB_CLONE Internal error : MESSAGE: sslu_descend - NULL sxp
AVSREQ-160842 DCP How to hide environment variables in filter ?
AVSREQ-162178 LP_1801 Phase-1: Support forces on retention FF (Full objects only) - Implementation
AVSREQ-172984 LP_1801 Hard IP terminal boundary UPF power model internal logic is getting corrupted
AVSREQ-139755 DMS_ELAB TYCMPAT error encountered in DMS/AMS simulation containing generate if-else block and assign statement in the else condition
AVSREQ-159867 SIM_SPARSE_ARRAY Major slowdown when dumping MDA between 20.12.t002 and 21.03.v003
AVSREQ-158301 RAND_GENERAL VALFIT warning incorrectly generated with a signed vector random variable in dist constraint
AVSREQ-165885 SPECMAN_COV Segmentation violation from syntax error in cover item expression
AVSREQ-99727 PARSE_SV -incdir option usage inside the library map file
AVSREQ-100991 GLS_GENERAL Enhancement to dump block level SDF annotation statistics.
AVSREQ-170006 ELAB_SV INTERR with optimizations disabled
AVSREQ-170243 PARSE_SV Gate-sim long simulation time cause by debug_opts indago_pp option
AVSREQ-171600 LP_1801 Always block is not getting triggered in power-on state after power shutoff
AVSREQ-172337 DEBUG_PROBE Waveform is not updating with new values even though testcase is finished successfully
AVSREQ-134899 COVERAGE_TOGGLE Smart refinement does not propagate from verilog vector to vhdl std_logic_vector
AVSREQ-133303 SPECMAN_COMPILE How to get load time of each loaded / translated file
AVSREQ-175966 SPECMAN_GENERAL Error : No notifications match : WARN_VERILOG_WIRE_UNDEFINED
AVSREQ-164581 SV_DPI UNSUAF error for DPI-C import: multi-dimension array of int is not supported
AVSREQ-162425 FUNC_SAFETY_CONCURRENT Memory usage issue of concurrent engine
AVSREQ-171288 DCP dcp core dumps instantly in 22.03-s001
AVSREQ-153040 ASSERTION_SVA xmvlog: *E,SFLNOS - Case-statement inside SVA is not supported
AVSREQ-178848 ASSERTION_DOC Please document -abv_disable_eos_eval
AVSREQ-172298 DMS_ELAB Xcelium crashes when probing dynamic objects in ADE UVM environment
AVSREQ-165003 ELAB_SV CUILLHIN Error occurrence at elaboration
AVSREQ-155613 XPROPAGATION_GENERAL XPROP causes hang at time 0 in always_comb
AVSREQ-162111 SIM_SV Behavior when x value is loaded into bit(2 state) with readmemh
AVSREQ-124764 SIMVISION_INFRA simvision hangs when parsing signal names that contain instance names like: sub1[0][0]
AVSREQ-166535 SIM_SV INTERR cod_wad_relocate enabling undo liverecorder
AVSREQ-164533 SIMVISION_MS TCL current probe doesn't show current immediately in Design Browser and Waveform Browser
AVSREQ-151526 LP_VPI LP trace cause of connect net in PA module does not result in UPF
AVSREQ-164721 DMS_PERF ams_digital_island_process_wrapper() adding 5 mins overhead
AVSREQ-146673 DMS_ELAB xmelab *E,CUNDCM : Error with Xcelium, works fine with competitor's logic simulator
AVSREQ-164990 LP_1801 automatic VDD/VSS connection in TB in LIBINLIB
AVSREQ-170318 SIM_CAPTURE_REPLAY Capture/Replay: xmsim crashes during replay for WAND nettype
AVSREQ-168812 LP_INFO_MODEL_AND_QUERY Xcelium is returning null values for upf_generic_sink using query commands.
AVSREQ-169060 VPI_GENERAL cbAtEndOfSimTime callback not filling in cb_data->time
AVSREQ-171729 LP_INFO_MODEL_AND_QUERY F,BCNOCP was caused by the wrong generation of bind_checker.sv
AVSREQ-165816 DMS_SIM Incorrect next_event_time returned from eurekaMixSynchronize call
AVSREQ-163123 DMS_AXUM SV bind with electrical fails when applied on multiple instances of same module
AVSREQ-169988 RAND_SOLVER Constraint solver failed when moved to 22.03 AGILE
AVSREQ-172757 FUNC_SAFETY_XFR xfr -fsv_ut: replicating Jasper checksum fix
AVSREQ-174613 COVERAGE_CODE Scoring Event in SOP Scoring Issue
AVSREQ-172311 RAND_SOLVER SAT timeout for particular seeds


CCRID Product Title
-------- ------------ ---------------------------
AVSREQ-130419 SIM_PERFORMANCE Verilog task calculation at time=0 is so heavy
AVSREQ-160770 LP_DOC callback objects are not updated when declared in UVM env.
AVSREQ-161501 SIMVISION_MS Add a way to display only analog or only digital signal object in design browser
AVSREQ-175828 LP_SIM_PERF "Power On Reset" Functionality Issue
AVSREQ-179364 SV_PARAMETERS Elab Internal error
AVSREQ-167359 SIM_SPARSE_ARRAY xmsim run time memory is 10 times more
AVSREQ-177197 SIMVISION_GENERAL It takes time till simvision is up. It looks for Indago_VB_SV Feature.
AVSREQ-175817 SIM_PERFORMANCE wire value not updated; running with default access permissions
AVSREQ-177048 GLS_PERFORMANCE Encountered "INTERNAL EXCEPTION Error", when added "-LPS_1801"option
AVSREQ-179060 SIMVISION_SIGNAL_TRACING Need a utility to filter currents and voltage above or below a certain threshold in SimVision measurement window
AVSREQ-167525 SIM_SPARSE_ARRAY Long test takes run time xmsim 10 times more memory than competition (now 1.4GB vs .7 GB)
AVSREQ-177305 SYSC_GENERAL Don't use COV01 to enable SystemC coverage
JIRA ID COMPONENT SUMMARY
AVSREQ-177865 SYSC_GENERAL Add support for -srcdir to resolve relative path issues.
AVSREQ-153376 GLS_SDF -sdfstats option shows timing check removed using tfile as unannotated
AVSREQ-175845 LP_TCL TCL: force -show does not explicitly display the source file path and its corresponding line number
AVSREQ-177307 SYSC_GENERAL Don't use covselect to enable SystemC coverage
AVSREQ-179392 LP_SV const SV struct gets corrupted


CCRID Product Title
-------- ------------ ---------------------------
JIRA ID COMPONENT SUMMARY
AVSREQ-181151 SPECTRE_AMSD dna_assembler always prints message saying using an old version of Spectre
AVSREQ-180491 DMS_ELAB xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-180556 DMS_ELAB crash during elaboration with message "vst_name() - invalid class, class 749"
AVSREQ-176380 SIM_SV_VHDL Issue with dynamic array of struct from SV to vhdl
AVSREQ-177287 SV_CODEGEN Unexpected : xmsim: *W,SYSFMW with 22.03-s03 $sformat
AVSREQ-178178 VSP_SIMULATION Exception error/crash while dumping the Profile report in NBRUN mode
AVSREQ-180911 DMS_ELAB FATAL: Segmentation fault during elaboration phase
AVSREQ-181044 DMS_LP_AMS AMS co-sim. crashes with internal exception in LP+MS - pwr_merge_nets
AVSREQ-179424 GLS_PERFORMANCE huge elaboration overhead when moving from ZD to SDF simulations


CCRID Product Title
-------- ------------ ---------------------------
AVSREQ-181977 VHDL_PERFORMANCE Xcelium BDOPT error with '-enable_vhdl_vect_opt_sens_sig'
JIRA ID COMPONENT SUMMARY
AVSREQ-102421 DMS_ELAB Example of using $SIE_input not behaving as expected
AVSREQ-172762 SIM_EVCD Evcd dump using tran primitive
AVSREQ-173805 DMS_ANALOG_ELAB analog_node_alias function aliases all bus bits as electrical for a mixed discipline bus
AVSREQ-171645 SPECTRE_AMSD SimulinkCoupler:Block Parameters Number of Pins Limit 0~100 But Circuit Over 100 Pins
AVSREQ-175500 ASSERTION_SVF xmvlog: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-180448 SPECTRE_AMSD Enhance connect modules to allow different delay for a rising and a falling edge
AVSREQ-176380 SIM_SV_VHDL Issue with dynamic array of struct from SV to vhdl
AVSREQ-171570 ASSERTION_SVF [Xcelium]Using "$past" in a "$display" statement [xmvlog:*F,INTERR]
AVSREQ-179712 VPI_PLI VPI error - Unexpected VST of type 738 in internal PLI routine ipi_findHandleInExpression.
AVSREQ-173004 IXCOM [EdgeCortix] xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-175577 GLS_PERFORMANCE Xcelium GLST simulation performance is slower than competitor


CCRID Product Title
-------- ------------ ---------------------------
AVSREQ-183419 ESW_ESWDBGEN xmsim: *E,ESWDBWRERR: Error occurred when generating esw.db
AVSREQ-180448 SPECTRE_AMSD Enhance connect modules to allow different delay for a rising and a falling edge
AVSREQ-180455 DMS_CONNECT_MOD timescale directives missing on all three EEnet_2_E IEs in the xcelium connect_lib
AVSREQ-171819 SIM_VHDL TRINDXC error
AVSREQ-177687 FUNC_SAFETY_CONCURRENT MESSAGE: sv_seghandler - trapno -1 addr(0x1a)
AVSREQ-180567 VPI_LWD Indago Missing connection from the parent scope
AVSREQ-177440 ELAB_BIND Need alternative for -top which is not controlled by config/any libmap rule
AVSREQ-177305 SYSC_GENERAL Don't use COV01 to enable SystemC coverage
JIRA ID COMPONENT SUMMARY
AVSREQ-179633 DMS_AMSD $temperature reports number just a bit too high
AVSREQ-177865 SYSC_GENERAL Add support for -srcdir to resolve relative path issues.
AVSREQ-178193 RAND_SOLVER Randomization fails on 22.09
AVSREQ-177307 SYSC_GENERAL Don't use covselect to enable SystemC coverage
AVSREQ-182432 SV_DATATYPES segfault during elab
AVSREQ-183109 RAND_SOLVER incorrect SystemVerilog constraint solver error
AVSREQ-176988 ELAB_PERF Corrupted directory names in tools. lnx86/inca/files/
AVSREQ-166099 ELAB_BIND CPF simulation : auto generated cds_amslps_psnconn_ams not found during elaborating design hierarchy
AVSREQ-184179 SPECTRE_AMSD Is there a way to get rid of parentheses surrounding net name in bundled port
AVSREQ-181743 VPI_GENERAL Incorrect object returned for textRef to a ref object in UVM
AVSREQ-182119 GLS_SDF Internal exception when elaborating netlist + SDF


CCRID Product Title
-------- ------------ ---------------------------
AVSREQ-185635 SPECTRE_AMSD Unexpected SFE-23 error from Spectre when instantiating arrays of cells in multi-step xrun
AVSREQ-153275 LP_DOC UPF documentation requires an update about -Simstate
AVSREQ-184907 LP_1801 Elaboration failed with internal exception with UPF
AVSREQ-186423 LP_DOC please correct the descriptin of set_simstate_behavior
AVSREQ-161501 SIMVISION_MS Add a way to display only analog or only digital signal object in design browser
AVSREQ-177197 SIMVISION_GENERAL It takes time till simvision is up. It looks for Indago_VB_SV Feature.
AVSREQ-179245 DEBUG_DESIGN_DATABASE Need assist to debug hard to reproduce DLCOIF error
AVSREQ-177967 MSIE_ELAB Internal exception after version up
AVSREQ-122847 GLS_TIMING tcheck usage wrong in user guide
AVSREQ-176408 IP_PROTECT_GENERAL xmprotect to be able to encrypt a gate-level netlist (.vg from vhelab) that includes a mix of encrypted and unencrypted RTL content
AVSREQ-185256 IXCOM Using -target with xrun -hw flow causes xmsim: *E,DLOALB runtime error when VHDL is involved
AVSREQ-177973 DEBUG_DESIGN_DATABASE Fatal during elaboration
AVSREQ-180630 IP_PROTECT_GENERAL AUTOPROTECT adding unwanted ' \ ' when encrypting macro in included file
AVSREQ-175446 IP_PROTECT_GENERAL xmprotect: *E,ENCERR: (test.vhd,0) Error during encryption. invalid or unknown or incomplete pragma specification '-pragma protect begin'.
AVSREQ-181508 SPECTRE_AMSD Regarding cds_internal_stub node signal introduced by simulator
AVSREQ-185126 COVERAGE_FUNCTIONAL coverage transition bins results in fatal internal error
JIRA ID COMPONENT SUMMARY
AVSREQ-186561 LP_ISOLATION Why does -exclude_elements not apply when location is fanout?
AVSREQ-168144 LP_DOC set_simstate_behavior syntax has an extra dash before DISABLE
AVSREQ-182432 SV_DATATYPES segfault during elab
AVSREQ-183131 DMS_SIM xrun simulation failure linked with multiple usage of $analog_node_alias command
AVSREQ-181859 DEBUG_DESIGN_DATABASE [Xcelium][22.09-s002]INTERNAL EXCEPTION when using -lwdgen
AVSREQ-184490 SIM_VHDL write in files from vhdl processes are sent to smartlog whereas it is not the case with verilog
AVSREQ-185188 DMS_LP_AMS AOILPE message does not point to any file or module
AVSREQ-183572 DMS_QUALITY Elaboration exits with vsto_class() - mixed bus, class 520


CCRID Product Title
-------- ------------ ---------------------------
AVSREQ-173802 SPECTRE_AMSD AMS Flex with Classic Spectre and certain save options results in incorrect real waveform in ViVA XL
AVSREQ-187155 DMS_AXUM During Mixed signal simulation, xrun fails with the ?xmelab: *F,INTERR: INTERNAL EXCEPTION? error
AVSREQ-187024 DMS_SIM xmsim: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-175962 LP_LIBERTY Xcelium elab unable to instrument liberty info from cdb to the HDL in low power build
AVSREQ-186955 LP_LIBERTY xmelab crash due to cdb file
AVSREQ-160278 ELAB_SV sv_seghandler - trapno -1 addr(0x7ffecd1a5ff8) during elaboration.
AVSREQ-180233 ELAB_SV xmelab MESSAGE: sv_seghandler - trapno -1 addr(0x7ffe42fd1ff8)
AVSREQ-181709 DMS_LP_AMS The error MPSSCN is reported incorrect for power model set on spice skeleton
AVSREQ-174399 LP_ISOLATION Missing isolation when using set_repeater
AVSREQ-187608 DMS_LP_AMS The analog signal inside SPICE netlist in control condition is not supported
AVSREQ-168861 DMS_ELAB internal exception building platform with AMS
AVSREQ-181982 SIMVISION_MS Flow probe is not added to waveform window
AVSREQ-188328 LP_LIBERTY ILLPRT error as .lib.cellindex.cdb.t is not created when CDS_IMPLICIT_TMPDIR is used
AVSREQ-145302 DMS_SIM AMS simulation leading to internal exception ssl_width_expr
AVSREQ-173947 DMS_ELAB RL_Bidir converts real to Z when replication operator is used
AVSREQ-184626 LP_LIBERTY ILLPRT as .lib.cellindex.cdb.t is not created
AVSREQ-164911 SIMVISION_GENERAL Order by time enhancement needed in open simulation form
AVSREQ-183749 DMS_LP_AMS Elaboration exits without proper message with UPF
AVSREQ-183729 ASSERTION_SIM SmartLog missing ASRTST
JIRA ID COMPONENT SUMMARY
AVSREQ-183472 LP_LIBERTY Xcelium report xmelab Internal Exception
AVSREQ-181401 LP_ISOLATION "-source -sink -no_isolation" does not work for split wire
AVSREQ-185458 LP_ISOLATION Elaboration with LP shows large degradation in elaboration time
AVSREQ-152412 SPECTRE_AMSD SFE-435 error with scalar signals defined with range [1:1]
AVSREQ-187470 VHDL_CODEGEN xrun: *E,VHLERR: Error during parsing VHDL file
AVSREQ-186545 LP_1801 21.03.013 works, 22.09.003 tool crash
AVSREQ-176507 LP_LIBERTY Enable xmlib2cdb to read cds.lib to place the index file in
AVSREQ-186256 SIM_SV svh_getpibforvstfromrtti - !rttip super internal exception when probing
AVSREQ-183572 DMS_QUALITY Elaboration exits with vsto_class() - mixed bus, class 520